发明名称 |
Fault tolerant computer system comprising a fault detector in each processor module |
摘要 |
In each module (11) of three or more central processor modules of a fault tolerant computer system, a detector (45) receives a comparator output signal and like comparator output signals from two adjacent modules and produces a detector output signal which confirms absence and presence of a fault in one of the above-mentioned each module. When the fault is confirmed, a controller or processor (49) isolates the module under consideration from the system by inhibiting delivery of a controlled output signal to a bus (31) and by connecting, with the module in question bypassed, switching units (53(1), 53(2)) of the adjacent modules. Preferably, one of the modules of the system is used as a master module of ordinarily delivering the controlled output signal to the bus with others used as checker modules of ordinarily inhibiting the delivery. When a fault appears in the master module, its controller delivers a module operation switching signal to the controllers of the checker modules to thereby substitute one of the checker modules for the master module subjected to the fault. |
申请公布号 |
US5485604(A) |
申请公布日期 |
1996.01.16 |
申请号 |
US19930145647 |
申请日期 |
1993.11.04 |
申请人 |
NEC CORPORATION |
发明人 |
MIYOSHI, HIROAKI;MIZUSHIMA, YASUHIKO;OHTSUKA, MAKOTO;HIHARA, HIROKI |
分类号 |
G06F11/18;G06F11/00;G06F11/16;G06F11/20;G06F15/16;G06F15/177;(IPC1-7):G06F11/34 |
主分类号 |
G06F11/18 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|