发明名称 MULTIPLYING CIRCUIT
摘要 PURPOSE:To perform multiplication in a short processing time by the multiplying circuit which obtains a product by multiplying a multiplier and a multiplicand represented in binary notation by each other and to make its scale smaller than that of a parallel multiplying circuit. CONSTITUTION:This multiplying circuit is equipped with a digit number detector 5 which detects the positions of '1' of the multiplier, a barrel shifter 7 which shifts the multiplicand to the left from low-order bits to high-order bits by the number of digits detected by the digit number detector 5, and an adder 8 which adds the multiplicands shifted by the barrel shifter 7 in order.
申请公布号 JPH086762(A) 申请公布日期 1996.01.12
申请号 JP19940139008 申请日期 1994.06.21
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 IMAKURUNUSHI NAOTAKA
分类号 G06F7/53;G06F7/52;G06F7/523 主分类号 G06F7/53
代理机构 代理人
主权项
地址