摘要 |
A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is provided in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. A wiring line, formed as a separate conductive layer, is provided in the stacking arrangement of the drive and load MISFETs of a memory cell for applying a ground potential to source regions of the drive MISFETs thereof.
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申请人 |
HITACHI, LTD. |
发明人 |
MEGURO, SATOSHI;UCHIBORI, KIYOFUMI;SUZUKI, NORIO;MOTOYOSHI, MAKOTO;KOIKE, ATSUYOSHI;YAMANAKA, TOSHIAKI;SAKAI, YOSHIO;KAGA, TORU;HASHIMOTO, NAOTAKA;HASHIMOTO, TAKASHI;HONJOU, SHIGERU;MINATO, OSAMU |