| 摘要 |
A pulse width discriminating circuit comprises an edge detecting circuit receiving an input signal for generating a detection signal when the input signal rises up, first to third counters each cleared by the detection signal and counting a different count clock, a capture register responding to the detection signal to store a count value of the first counter, an arithmetic operation circuit for multiplying the stored value in the capture register with a predetermined constant number, and a compare register storing the result of the multiplication operation performed in the arithmetic operation circuit. First to third comparators are provided each comparing the stored value of the compare register with a count value of a corresponding one counter of the first to third counters for generating a coincidence signal, and each of a plurality of latch circuits responds to the coincidence signal of a corresponding comparator of the first to third comparators to latch a level of the input signal.
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