An integrated switch with ports for connection to peripheral devices and switching apparatus for selective switching in frame formats between ports, each port occupying a fixed timeslot. The signals are in full or half-fulf format. Each time slot has a memory address in a multi-fram information memory with memory cells at memory locations. A writer pointer designates a memory location. The port arranged in groups associated with a peripheral devices. A plurality of processors associated with a system having a backplane with mutiple groups.
申请公布号
CA2151292(A1)
申请公布日期
1995.12.11
申请号
CA19952151292
申请日期
1995.06.08
申请人
WEIR, STEVEN P.;BELL, KAREN;MONTESCHIO, JOHN;MUEGGE, SHAD H.;HENDERSON, PAUL A.;STOLP, MARK D.
发明人
WEIR, STEVEN P.;BELL, KAREN;MONTESCHIO, JOHN;MUEGGE, SHAD H.;HENDERSON, PAUL A.;STOLP, MARK D.