| 摘要 |
PURPOSE:To provide an image processing circuit which enlarges images read out of plural memories into well-balanced images by converting the parallel data of the read images into serial data. CONSTITUTION:A D/A conversion clock CK is supplied to a D/A converter 8, an optional frequency dividers 1, and a 1/4 frequency divider 2. The optional frequency divider 1 supplies an OR gate 3 with the clock generated by dividing the frequency of the clock CK at a specific frequency division ratio and also supplies it to the 1/4 frequency divider 2 to reset it. The 1/4 frequency divider 2 supplies the clock generated by dividing the clock CK by 4 to an OR gate 3 in a period wherein it is not reset. The OR gate 3 supplies the OR output between both the supplied clocks to both memories 6a and 6b to read the image data out in parallel, and supplies them to a P/S converter 7, which converts the data into serial data. The D/A converter 8 performs the D/A conversion of the serial data and displays the result as an image at an unillustrated display part. |
