Computational circuit based on capacitor arrays

摘要

A circuit for generating a signal indicative of the result of the computation The circuit includes a plurality of signal input lines, for receiving voltages proportional to Si. The summation is performed on a first charge integration circuit having an input terminal and elements for generating an output signal indicative of the total charge received on the input terminal. The input terminal is held at a reference potential independent of the charge input thereto. The weight signals values are generated on a first capacitor network includes a plurality of capacitors, each capacitor having a top electrode and a bottom electrode. Each top electrode is connected to one of the signal input lines and each bottom electrode is connected to the input terminal of the first charge integration circuit. The capacitor connected to the signal line corresponding to Si has a capacitance proportional to ai if ai>/=0. If any of the ai values is negative, a second charge integration circuit and a second capacitor network is included in the circuit. The second charge integration circuit also has an input terminal and circuitry for generating an output signal indicative of the total charge received on the input terminal. The input terminal of the second charge integration circuit is also held at the reference potential independent of the charge input thereto. The second capacitor network also includes a plurality of capacitors, each capacitor having a top electrode and a bottom electrode. Each top electrode is connected to one of the signal lines and each bottom electrode is connected to the input terminal of the second charge integration circuit. In the case in which one of the ai>/=0, the capacitances are chosen such that the difference in the capacitance values of the capacitor in said first capacitor network and said capacitor in said second capacitor network connected to the signal line corresponding to Si is proportional to ai. A difference circuit generates a signal indicative of the difference in the output signals generated by the first and second charge integration circuits to provide the value F.