| 摘要 |
<p>PURPOSE:To realize a wave pipeline transfer and speed up the data transfer in a bus type or star type data transfer device by adjusting data skew which is a factor of limitations on the shortening of a transfer cycle. CONSTITUTION:In the latche array 131 of a reception device 102a, latches 301 which are connected in series similarly to a shift register latch and hold received data having data skew temporary for several cycles over different phases of a clock PHI0. A selector 303 selects the output of those latches 301 so that the output is in phase with the clock PHI0, and then inputs the output to a data reception part 132. A clock PHI1 is used for the metastable evasion of the latches 301a. In the adjusting operation, the settings of selectors 302-303 are held in a selector map 134 and in normal operation, switching from those values to optimum settings is performed corresponding to a transmission device 101. The data skew of the bus type data transfer device having plural transmission devices can be reduced.</p> |
