发明名称 Central processing unit address pipelining
摘要 A microprocessor for use in a computer system which pipelines addresses for both burst and non-burst mode data transfers. By pipelining addresses, the microprocessor is able to increase the throughput of data transfers in the system. In the present invention, bits are used which may be programmed to disable and enable the address pipelining for the non-burst mode and burst mode transfers.
申请公布号 US5469544(A) 申请公布日期 1995.11.21
申请号 US19920973720 申请日期 1992.11.09
申请人 INTEL CORPORATION 发明人 AATRESH, DEEPAK J.;NAKANISHI, TOSAKU;MATHEWS, GREGORY S.
分类号 G06F13/42;(IPC1-7):G06F13/00 主分类号 G06F13/42
代理机构 代理人
主权项
地址