发明名称 |
Circuit for clamping enable clock in a semiconductor memory device |
摘要 |
A circuit for a clamping an /RAS signal in a DRAM. The bit line pre-charge generator is activated after the set-up of the VBB voltage, so that /RAS signals may be supplied to the chip after the bit line pre-charge voltage (VBLP) has reached the desired level, thereby preventing malfunction of the sense amplifiers. The circuit includes: a VBB sensor for producing VBB set-up signal S1 when a back bias voltage VBB in the semiconductor memory device has reached a desired level; a power-up generator for producing a power-up signal S2 when power in the semiconductor memory device is set-up; a VBLP generator for generating a bit line pre-charge voltage VBLP; a VBLP controller for holding the VBLP voltage to a ground voltage level according to the S1 and S2 signals; a VBLP sensor for generating VBLP set-up signal S3 when the VBLP voltage has reached a desired level; a /RAS pass signal generator for producing a /RAS pass signal S4 according to the S3 and S2 signals; a NOR circuit for controlling the transmission of the /RAS signals according to the S 4 signal.
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申请公布号 |
US5469387(A) |
申请公布日期 |
1995.11.21 |
申请号 |
US19930125953 |
申请日期 |
1993.09.23 |
申请人 |
GOLDSTAR ELECTRON CO., LTD. |
发明人 |
KIM, TAE-HOON |
分类号 |
G11C11/41;G11C5/14;G11C7/12;G11C7/22;G11C8/18;G11C11/408;G11C11/409;(IPC1-7):H03K5/08;G11C7/00 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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