| 摘要 |
<p>PURPOSE:To improve the reliability in the receipt and delivery of data between circuits by realizing a bit buffer circuit which is capable of overlaying data without any omission of data when the data are overlaid on internal frame pulses and clocks. CONSTITUTION:In a bit buffer circuit, a single D-FF (hereinafter referred to as D-FF [0]) is provided in addition to a D-type flip flop group (D-FF group) composed of n D-type flip flops (D-FF). Input data are supplied to the data terminal and a priority processing circuit is provided. The priority processing circuit where a reading frame pulse is preferentially outputted, the pulse that a decoder having the same phase as the reading frame pulse outputs is suppressed and the pulse of the decode signal which is not the same in phase as the reading frame pulse is outputted is provided. The output of the priority processing circuit is defined as the select signal of a selector and the outputs of the single D-FF [0] and D-FF are selected.</p> |
