INTEGRATED CIRCUIT COMPRISING AN OUTPUT STAGE WITH A MILLER CAPACITOR

摘要

An integrated circuit, comprising an output stage with an input (I) which is coupled to a first and a second gate of an NMOS transistor (N1) and a PMOS transistor (P1), respectively, and an output which is connected to a first (Vdd) and a second supply terminal (Vss) via the PMOS transistor and the NMOS transistor, respectively. The output is coupled to the first gate via a series connection of a Miller capacitor (CMN) and switching means (N2, N3). The Miller capacitor limits the rate of increase of the voltage on the output, thus preventing interference. The switching means are rendered non-conductive ahead of the switching over from logic low to logic high. This prevents sudden discharging of the Miller capacitor which would otherwise cause interference itself.