| 摘要 |
a violation detecting circuit for decoding first and second binary code data and detecting the violation bit; a data mixing circuit for mixing the first and second binary code data; a first selection latch circuit connected to the output terminals of the violation detecting circuit and data mixing circuit, for selecting one of the output data of the data mixing circuit and predetermined logic state of data and shifting it by 1 bit according to the result of the violation bit detection; a second selection latch circuit connected to the output terminals of the violation detecting circuit and first selection latch circuit, for selecting one of the output data of the first selection latch circuit and predetermined logic state of data and shifting it by 1 bit; a third selection latch circuit connected to the output terminals of the violation detecting circuit and second selection latch circuit, for selecting one of the output data of the second selection latch circuit and predetermined logic state of data and shifting it by 1 bit and at the same time outputting it as a binary information decoded by B3ZS decoding mode; a fourth selection latch circuit connected to the output terminals of the violation detecting circuit and third selection latch circuit, for selecting one of the output data of the third selection latch circuit and predetermined logic state of data and shifting it by 1 bit; a fifth selection latch circuit connected to the output terminals of the data mixing circuit and fourth selection latch circuit, for selecting the output data of the data mixing circuit if AMI decoding mode is set by a mode selection signal, and selecting the output data of the fourth selection latch circuit if HDB3 decoding mode is set.
|
