A QUASI-PASSIVE SWITCHED-CAPACITOR (SC) DELAY LINE

摘要

A quasi-passive switched capacitor delay line includes a predetermined number of passive switched capacitor delay stages (Q1/Q2/C1, Q3/Q4/C2, Q5/Q6/C3, Q7/Q8/C4) and an amplifier (A1). The control terminal of each first transistor (Q1, Q3, Q5, Q7) in each delay stage receives a unique clock phase and the control terminal of each second transistor (Q2, Q4, Q6, Q8) of the same stage receives a different clock phase wherein the clock phase received by each second transistor is delayed by two clock cycles from the clock phase received by each respective first transistor.