DATA PROCESSOR PROVIDED WITH PLURALITY OF ON-CHIP MEMORY BUSES

摘要

PURPOSE: To allow a data processing unit to access two memory locations in an address space simultaneously by multiplexing in time the content of memory location addressed respectively by 1st and 2nd memory address buses on a memory data bus. CONSTITUTION: The parallel characteristic of auxiliary arithmetic logic units(ARAU) 52a, 52b is calculated by a CPU with memory addresses more than one within a single machine cycle. Thus, a data bus controller 56 can connect a data line 30d of a data bus line to CPU buses 60a, 60b and register buses 62a, 62b more than the unity within a single machine cycle. The controller conducts control of application of outputs of the ARAUs 52a, 52b to the data line 30d via the address lines 30a, 30b and time multiplexing of data of the data line 30d with respect to an internal bus of the CPU based on an executed instruction code.