Semiconductor memory device having built-in test circuits selectively activated by decoder circuit

摘要

A dynamic random access memory device internally carries out inspection sequences in a diagnostic mode of operation, and an instruction circuit incorporated therein discriminates a Write-CAS-Before-RAS entry cycle for simultaneously supplying test enable signals indicative of inspection sequences to internal test circuits, wherein the instruction circuit firstly decodes a multi-bit instruction signal and repeatedly produces a latch control signal for sequentially storing the decoded signal so that a plurality of test enable signal are simultaneously supplied to the test circuits.