发明名称 |
Method of making semiconductor integrated circuit having isolation oxide regions with different thickness |
摘要 |
A method of manufacturing a semiconductor memory device having a peripheral circuit portion, the operating voltage of which is relatively high and a memory array portion, the operating voltage of which is relatively low comprises the steps of forming an inversion preventing layer on the peripheral circuit portion, forming an oxide layer for isolation between-devices adjacent thereto, forming on the memory array portion the inversion preventing layer, the impurity concentration of which is higher than that of the peripheral circuit portion and forming the oxide layer on the peripheral circuit portion at the same time that the oxide layer for isolation between devices is formed adjacent thereto.
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申请公布号 |
US5466623(A) |
申请公布日期 |
1995.11.14 |
申请号 |
US19940296940 |
申请日期 |
1994.08.29 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
SHIMIZU, MASAHIRO;TSUKAMOTO, KATSUHIRO |
分类号 |
H01L21/762;(IPC1-7):H01L21/823 |
主分类号 |
H01L21/762 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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