| 摘要 |
<p>PURPOSE:To provide a synchronous circuit capable of preventing malfunction due to clock skew without performing substantial layout correction. CONSTITUTION:In this synchronous circuit for which data latched to a flip-flop 1 in synchronism with input clock signals CK1 are delayed in a logic circuit 4 and latched to the flip-flop 2 of a next stage in synchronism with clock signals CK2 for which the input clock signals are delayed for prescribed time in a clock delay system 3, a data transmission system between the flip-flops 1 and 2 is provided with a variable delay circuit 10 capable of inputting control signals CTL from an outside through a delay control line DCL and selecting delay time corresponding to the level. Thus, the layout correction during design and after the design is eliminated or suppressed to minimum and the malfunction due to the clock skew is prevented.</p> |
