Method of increasing the data-processing speed of a signal processor

摘要

An apparatus and method increase the data-processing speed of a signal processor whose signal-processing unit includes at least one arithmetic logic unit and one multiplier which are fed with input data of n-bit word length. When such a signal processor is supplied from a source with input-data words having a shorter word length than the maximum word length of n bits of the signal processor, invalid bits are masked during the loading process. The loading operation is accelerated by changing the contents of the input-data words using a mask value in at least one presettable masking unit before the input-data word is processed by the signal-processing unit.