| 摘要 |
PURPOSE:To reduce the circuit scale of a QPSK synchronizing circuit and to make the circuit scale suitable to miniaturize the circuit and to make it into IC. CONSTITUTION:An IF signal is distributed into two by a distributor 1, the output of a VCO 2 is modulated by the orthogonal local signal obtained by a 90>= - distributor 3 and balance modulators 4-1 and 2, and an I signal and a Q signal are obtained through LPF 5-1 and 2. Binary shaping is performed for these I and Q signals in comparators 6-1 and 2, and signals (i) and (q) are outputted. The size comparison of the 1 land Q signals and the size comparison of I and (-Q) signals are performed and the output of a signal EX-OR (9-2) is obtained. The output (9-3) of the exclusive OR of the output of the EX-OR (9-1) and EX-OR (9-2) of the signals Li) and (,q) is made the input of the control voltage of the VCO 2 via a loop filter 10. |
