Translator Chip for a Wideband Network

摘要

Translator chip for a wideband network, consisting of a circuit configurated starting from an input step (1); a detector of empty cells and a filter (2); a step of control calculus (3); an extractor of the page address (4); a header processor (5); a delay step (18); an output step (6); an interface with microprocessor (7); an insert step (8); an interface of outer memories (9); and an extraction step (10), the header of the data flow cells (11) modifying the input step, by adapting them in order to implement the functions of the MTA layer for the data processing, while the header processor (5), in collaboration with the outer memories (13) performs the translation of the cell headers in accordance with the programming shown for the network element where it is found.