发明名称 PARALLEL COMPUTER
摘要 <p>PURPOSE:To secure the consistency of contents between a cache in a reception processor and a memory and to eliminate the need of making the communication area, where messages are written, resident in the memory in the case of the method where messages to be transferred between user processes are directly written in the communication area assigned to the transmission destination process. CONSTITUTION:When a message is received, the message header is written in a memory 4 by a memory write circuit 251, and the OS issues a cache flash instruction which designates the communication area designated by this message header. A cache memory 11 which is flashed by this instruction is used, and data belonging to this communication area is made invalid. If this data is updated after being read out from the memory 4 to the cache memory 11, it is written back to the memory 4. If the communication area is paged out of the memory 4, the OS reserves the communication area designated by the message header in the memory 4.</p>
申请公布号 JPH07262150(A) 申请公布日期 1995.10.13
申请号 JP19940053401 申请日期 1994.03.24
申请人 HITACHI LTD 发明人 HIGUCHI TATSUO;NAKAKOSHI JUNJI;ISOBE TADAAKI;ANDO TOSHIMITSU;IWASAKI MASAAKI;ISHII MASAHITO;KATO SHINICHI;PATORITSUKU HAMIRUTON;ISHIYAMA AKIRA;INAGAMI YASUHIRO
分类号 G06F15/17;G06F12/08;G06F15/163;(IPC1-7):G06F15/163 主分类号 G06F15/17
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