Defect address memory circuit for semiconductor memory device

摘要

The circuit has charge nodes connected in parallel with electrical fuses, each supplied with current in response to a defect address memory signal, provided in response to an external control signal. A redundant read amplifier provides a redundant block activation signal, for replacing a defect address in response to a logic level of the charge nodes and a control, activated by the memory signal of the defect address, decodes a received address signal to provide a current path through a selected fuse.