Interface circuit for controlling data transfers

摘要

An interface circuit for a peripheral device is disclosed that can accurately cope with any host with the same hardware whether the host is in the pre-read mode or the post-read mode and can send an interrupt request to the host practically without a waiting time if the host is in the post-read mode. The interface circuit generates an interrupt request (IRQ) to a host in response to a data request (DRQ) from a peripheral device (HDD) and drops the interrupt request if the status of the peripheral device is read by the host; it detects that the host operates in a post-read mode, and responds to the post-read mode detect signal and the status reading by the host in order to enable the regeneration of the interrupt request to the host.