发明名称 |
NONVOLATILE SEMICONDUCTOR MEMORY CELL ARRAY, METHOD FOR EXECUTION OF OPERATION OF MEMORY CELL IN NONVOLATILE SEMICONDUCTOR MEMORY CELL AND METHOD FOR EXECUTION OF ERASURE OPERATION |
摘要 |
<p>PURPOSE: To provide non-volatile semiconductor core memory performance which is reinforced by reducing stress on a core memory cell. CONSTITUTION: The stress is reduced by selectively impressing a bias voltage to a read line 13 under the control of a word line 19. The word line is connected to an inverting element, and this element is connected to a transistor for grounding the gate of a variable threshold value transistor 11b at a memory cell 11. The synchronous power down of the read line is reflected with the power down of the word line. Further, in case of power down, a sense amplifier 29 for the specified core memory cell is disconnected from a master latch circuit 112, and that amplifier is connected to a slave latch circuit 114 for guaranteeing data sensed by the core memory during a read operation and applies a preceding sense amplifier output to an I/O buffer 116. Moreover, a word line voltage during the erasing operation at the read line and the variable threshold value transistor is reduced.</p> |
申请公布号 |
JPH07254295(A) |
申请公布日期 |
1995.10.03 |
申请号 |
JP19950006544 |
申请日期 |
1995.01.19 |
申请人 |
ATOMERU CORP |
发明人 |
JIYOOJI SUMARANDOYUU;SUTEIIBUN JIEI SHIYUUMAN;TSUNNCHIN UU |
分类号 |
G11C17/00;G11C16/02;G11C16/04;G11C16/06;G11C16/08;(IPC1-7):G11C16/06 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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