| 摘要 |
<p>PURPOSE:To reduce the capacity of memory in use, reduce the size, and obtain economical advantages by writing addresses of 1st memory storing pixel data of non-zero coefficients in a 2nd memory, rearranging them in specific order, calculating the number of successive 0 s present between the pixel data of non-zero coefficients on the basis of the addresses and combining them with the man-zero coefficients. CONSTITUTION:The pixel data are written in the addresses of RAMs(A) 28a and 28b corresponding to zigzag scanning order, the addresses of the non-zero coefficients of the pixel data are written in RAMs (B) 31a and 31b, and the addresses in the RAMs (B) 31a and 31b are rearranged in the increasing order. The pixel data of the non-zero coefficients are read out of the RAMs (A) 28a and 28b on the basis of the rearranged addresses, the number of zero runs is calculated by using the addresses read out of the RAMs (B) 31a and 31b, and the non-zero coefficients are combined. Consequently, the circuit functions even as a buffer memory.</p> |
