TIME SERIES SYNCHRONOUS CIRCUIT FOR PARALLEL PROCESSING DECODER

摘要

PURPOSE:To provide the time series synchronous circuit of the parallel processing decoder capable of guiding decoded signals into a state of time series synchronization at the time of time series step out. CONSTITUTION:The channel superimposing codes separated by a demultiplexer 2 into serial superimposing code series are supplied to Vitabi decoders V1-V6. A stepout signals to be outputted from the Vitabi decoders V1-V6 are ORed by an OR arithmetic circuit 3 and are supplied to the synchronization control circuits of the Vitabi decoders V1-V6. The output of the stepout signals in the prescribed period from the Vitabi decoders V1-V6 is detected by a time series stepout circuit 4 and a shift signal is generated by each detection. Based on the shift signal, the first code of the n code series in succession in the serial superimposing code series to be sent for the separation of the demultiplexer 2 is changed by a timing shift circuit 1 in succession to make the time series synchronization state.