| 摘要 |
Two devices HR and FR are coupled to a bus with a common memory via a port controller. Device HR requires a high (or maximum) average rate of access, device FR requires a fast response (minimum latency) in establishing access. Request signals HRQ, FRQ from the devices are latched by latches 20 and 21, passed as HRX, FRX through an arbitration or resolver circuit 22 as HRY, FRY to a sequence control unit 23 to initiate an access cycle. Cycle timing is determined by a delay line timebase circuit 24, which responds to a single change of level of a signal DLY (in either direction). Latch 21, when set, generates an request pending signal FRRP which is fed to the HR device to cause it to increase its cycle length so that the FR access cycle will finish before the next HR access cycle is initiated.
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