| 摘要 |
A frequency synthesizer has the configuration of a phase locked loop (PLL) having a voltage controlled oscillator (VCO) generating an output signal, a phase detector for outputting a control signal to the VCO, and circuitry coupled to an output port the VCO for offsetting the frequency of a sample of the output signal. The synthesizer includes a sampling mixer operative with a source of reference signal and interconnecting the offset circuitry with the phase detector. The sampling mixer mixes the offset sample with the reference signal to output a comb frequency spectrum of signals differing in frequency from each other by multiples of the reference frequency. A filter selects a signal outputted by the sampling mixer at one of the comb frequencies for application to the phase detector. The phase detector is operative with a source of input signal having an input signal frequency for phase locking with the signal selected by the filter. The PLL includes a stabilizing loop filter circuit preceding the VCO and having means for adjusting a value of the control signal to tune the frequency of the output signal. In the offset circuitry, inphase and quadrature portions of the output sample are mixed with either the reference frequency or a fraction thereof, as selected by a switch, and are summed to provide the offset frequency sample to the sampling mixer.
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