SPARE DECODER CIRCUIT OF MEMORY DEVICE

摘要

The spare decoder circuit for a memory device comprises a programmable fuse ROM array composed of a plurality of programmable fuse ROMs, each having a fuse connected to a power at one terminal, a field effect transistor having a source connected to the other terminal of the fuse and a drain connected to a ground and an inverter having an input terminal connected to a contact point of the fuse and field effect transistor and an output terminal connected to a gate of the field effect terminal; and a comparing circuit for comparing the output signal of the fuse ROM array with an address input signal and outputting one signal.