| 摘要 |
The disclosure relates to analog-digital converters. It is sought to limit the power consumption and obtain a better compromise among the different performance characteristics of the computer. In a general structure of a converter there are, firstly, a coarse converter for the most significant bits and, secondly, a fine converter for the least significant bits. One of them, generally, the fine converter, has differential amplifiers [AD(1) to AD(N)]receiving the voltage to be converted (Ve) and a reference voltage. It is proposed to place sample-and-hold circuits [EB(1) to EB(N)] at output of these differential amplifiers and to eliminate the sample-and-hold circuit that is often placed upline with respect to these amplifiers.
|
