发明名称 |
Branch prediction and resolution apparatus for a superscalar computer processor |
摘要 |
An apparatus and method for improving the performance of superscalar pipelined computers using branch prediction and verification that the predicted branch is correct. A predicted branch may be resolved in one of two distinct pipeline stages, and a method is provided for handling branches that are resolved in either of the pipeline stages. A branch verification method is provided that verifies that the architecturally correct instructions are in the decode and execution stages. Furthermore, two sets of prefetch buffers are provided to allow branch prediction when multiple clock decoding is required by a multi-clock instruction. |
申请公布号 |
US5442756(A) |
申请公布日期 |
1995.08.15 |
申请号 |
US19920922855 |
申请日期 |
1992.07.31 |
申请人 |
INTEL CORPORATION |
发明人 |
GROCHOWSKI, EDWARD T.;ALPERT, DONALD B.;MILLS, JACK D.;WEISER, URI C. |
分类号 |
G06F9/318;G06F9/38;(IPC1-7):G06F9/38 |
主分类号 |
G06F9/318 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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