发明名称 Common breakpoint in virtual time logic simulation for parallel processors
摘要 A logic simulator is distributed over a plurality of processing nodes for simulating a circuit. A plurality of logic simulation programs execute on respective ones of the nodes, and simulate respective parts of the circuit. Each of the logic simulation programs executes at its own pace, and either receives an input from or supplies an output to another of the nodes. Each of the logic simulation programs also predicts an input when unavailable from another of the nodes. A host broadcasts a breakpoint time to all of the nodes. A plurality of logic simulation controllers execute on respective ones of the nodes, and direct storage of nets and/or states of the logic simulation programs. Each of the logic simulation controllers receives the breakpoint time from the host and reports to the host when the respective logic simulation program has advanced to or past the breakpoint time. When all of the nodes have reported that their respective logic simulation programs have advanced to or past the breakpoint time, this means that nets and states at the breakpoint time are valid. Then, the host obtains from one or more of the nodes values of one or more nets and/or states at the breakpoint time. In another mode of operation, before broadcasting the breakpoint time, the host sends to one of the nodes responsible for generating a condition or event a request to notify the host when the condition or event occurs and a local virtual time that the condition or event occurred. The host then broadcasts the local virtual time as the breakpoint time.
申请公布号 US5442772(A) 申请公布日期 1995.08.15
申请号 US19920993142 申请日期 1992.12.18
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 CHILDS, PHILIP L.;RADIA, NIMISH S.;SKOVIRA, JOSEPH F.
分类号 G06F11/26;G06F13/40;G06F15/173;G06F17/50;H04L1/00;H04L7/033;H04L12/18;H04L12/56;H04Q11/00;H04Q11/04;(IPC1-7):G06F15/16 主分类号 G06F11/26
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