| 摘要 |
PURPOSE:To improve the level of integration, reduce the power consumption of an SRAM, optimize the load element of the memory cell of the SRAM, and prevent the soft error of the SRAM. CONSTITUTION:In an SRAM, gate electrodes 7, 14 of MISFET's Qd1, Qd2 for loads connected with the drain regions 17B of MISFET's Qd1, Qd2 for driving are formed above the MISFET's Qd1, Qd2 for driving memory cells. The channel forming regions 17A, the source regions 17C and the drain regions 17B of the MISFET's Qd1, Qd2 for loads are formed, via gate insulating films 5, 15, above the gate electrodes 7, 14 of the MISFET's Qd1, Qd2 for loads. By the above means, it becomes possible that the flip-flop circuit of the memory cell is turned into a perfect CMOS type and the ratio of the current quantity at the time of operating of the load element to the current quantity at the time of waiting of the load element is increased. Hence the power consumption can be reduced. Since the MISFET's for loads are formed above the MISFET's for driving, the memory cell area is reduced, and the high level integration of an SRAM is realized. |
