发明名称 FAILURE PROCESSING SYSTEM FOR MULTIPROCESSOR
摘要 PURPOSE:To prevent the production of system down for the entire system from the failure of one processor, by introducing the centralized supervisory control to the multiprocessor. CONSTITUTION:CSC8 is connected to the processor 11-n with the centralized control bus 9 the common bus 3. If a failure is taken place to a processor Pui or the memory 2i connected to it, it is detected 10i in Pui and it is told to CON 21 of CSS8. The circuit 21 analyzes the cause to failure and it stops the failed Pui and disconnect the bus 3, if it is heavy failure. The circuit 21 reads in the registers 11 to 13 representing the condition of failure taken place, stores it in the register 22 and displays 23. Next, the content of the registers 23 and 22 is controlled 21 and is delivered to the common bus. The PU can read in this, which can start the failure processing analysis program among normal PU and performs failure processing analysis. Thus, the working efficiency can remarkably be increased.
申请公布号 JPS5471537(A) 申请公布日期 1979.06.08
申请号 JP19770137901 申请日期 1977.11.18
申请人 HITACHI LTD 发明人 YAMAGUCHI KOICHIROU;NISHIMURA KAZUO
分类号 G06F11/20;G06F11/00;G06F15/16 主分类号 G06F11/20
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