| 摘要 |
PURPOSE: To accurately predict the existence of a branching instruction by providing a branching target buffer circuit for indexing a branching target buffer cache, while using an instruction pointer and for searching the branching instruction to appear based on the instruction pointer. CONSTITUTION: A memory and bus logic 35 attempts to input or storage to a high-speed cache memory. An instruction fetch unit 30 maintains a current fetch address while using the instruction pointer, and a microprocessor instruction is supplied to the head of a pipeline. When an instruction decoder 60 discriminates the received microprocessor instruction as a branching instruction, the instruction decoder 60 sends information describing that branching instruction to a branching address calculator 50, in order to perform special processing. If a branching target buffer circuit 40 predicted branching concerning that branching instruction, the branching address calculator 50 verifies that branching prediction, if possible, by using the branch information received from the instruction decoder 60. |
