| 摘要 |
<p>PURPOSE:To prevent over writing and over erasing of a flash EEPROM. CONSTITUTION:Writing (or erasing) data of logic 1 (or 0) is repeated plural times for a memory cell (m pieces) of an address N of a memory (DUT) to be tested, of which input data is constituted with (m) (m>1) bits, and when writing (erasing) operation is finished, a PASS signal of an H level is inputted to a (m) input AND gate from corresponding logical comparator SC1-SCm, an output of an H level of the gate is fed back to a second input terminal of a two input AND gate corresponding to a signal distribution section VD, and the gate is closed. From the point of that time, a write enable signal WE supplied from a signal generating section FC is not applied to a DUT already written (or erased), further writing (or erasing) operation is not performed. In order to make any bits of 1, 4, 8 bits of input/output data of the DUT possible to be tested, the device is constituted so that arbitrary output of SC1, AND4, AND8 is selected by a selector, and can be fed back to the two input AND gate corresponding to the logical comparator.</p> |
