METHOD AND CIRCUIT FOR ROW REDUNDANCY OF SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE: To provide a row redundancy circuit high in redundancy and capable of improving yield in a semiconductor memory device adopting a double row decoder. CONSTITUTION: Fuse boxes 46 and 48 are respectively provide for spare row decoders 42 and 44 arranged on both sides of a memory cell array block 32. Row address signals inputted to main row decoders 38 and 40 are set to be inputs and control signals RED1 and RED2 operating the spare row decoders at the time of designating a defective address with a redundant program by a fuse are outputted. A row redundancy control circuit 50 suppresses the operation of the main row decoders in accordance with the control signals RED1 and RED2 and operates the spare row decoders. When the word lines 52A, 52B and 56A and 56B of the row decoder 38 have shorting defect in a former case, the spare row decoder 44 cannot be used and redundancy cannot be executed but the spare row decoders 42 and 44 can be operated, redundancy can be executed and redundancy efficiency improves.