Output circuit for semiconductor memory device realizing extended data output upon inactivation of CAS signal

摘要

In an output circuit for a semiconductor memory, configured to continue to output a memory data even if a column address strobe signal supplied from an external device to the semiconductor memory is disabled, a logic circuit receiving the column address strobe signal generates a latch signal which is inactivated immediately when the column address strobe signal is enabled but which is activated with a delay when the column address strobe signal is disabled. A latch circuit latches a read amplifier output signal in response to the latch signal, and an output buffer receives an output of the latch circuit to output a data signal.