STATIC DISCHARGE PROTECTIVE CIRCUIT

摘要

PURPOSE: To avert an electrostatic discharge current pulse from a sensitive integrated circuit structure and to regulate the threshold discharge voltage at the time of fabricating an integrated circuit by providing a circuit for triggering an silicon controlled rectifier(SCR) circuit utilizing the SCR latch-up effect occurring in CMOS process. CONSTITUTION: A trigger circuit comprising an inverter 30 for driving the gate of an NMOS trigger FET 18 in response to an ESD phenomenon at an I/O pad 15 is provided as an electrostatic discharge(ESD) protective circuit. The inverter 30 comprises a PFET 40 and an NFET 42 connected in series between the pad 15 and the circuit earth. At the time of ESD phenomenon, a supply voltage VDD to the entire chip has the ground level and the gates of the PFET 40 and an NFET 42 are earthed. As the electrostatic discharge progresses at the I/O pad 15, the PFET 40 begins to be conducted and connected with the gate of an NMOS trigger FET 18 to cause latching through an SCR.