| 摘要 |
<p>A computer system (44) including a central processing unit (CPU) (46) and a power management circuit (PMC) (52). The CPU (46) has an active mode where it is responsive to interrupt and direct memory access requests, and a standby mode where it is in a low power state and is not responsive to the interrupts and direct memory access requests. The PMC (52) monitors the interrupts and direct memory access requests in the system (44) when the CPU (46) is in the standby mode, and causes the CPU (46) to enter the active mode upon the detection of either an interrupt or a direct memory access request. The PMC (52) includes: a standby register having a content which indicates either a standby or an active mode for the CPU; logic coupled to the standby register to produce a standby enabling output signal when the content of the standby register indicates a standby mode, and to produce a standby disabling output signal when the content of the standby register indicates an active mode; and logic which forces the content of the standby register to the active mode upon the detection of either an interrupt or a direct memory access request. A method for managing power consumed by a CPU (46) of a computer system (44) includes forcing the CPU (46) to enter a low-power standby mode, monitoring the computer system (44) for interrupts and direct memory access requests, and reactivating the central processing unit (46) to an active mode where the CPU (46) is capable of responding to the detected requests. <IMAGE></p> |
