| 摘要 |
The memory has storage elements located at the intersection points of rows and columns (15,19) and addressed via a multi-bit address fed to a decoder circuit having row and column decoders (12,14), controlling selection switches (16). Each row line (15) is coupled on the side of the matrix opposite to the row decoder (12) to a different line of a test bus (21). Each column line (19) is coupled to one line of the test bus on the side of the memory matrix opposite to the selection switches (16). Pref. the row and/or column lines are coupled to the test bus via respective test switches (20,22), controlled via a common test signal. |
