| 摘要 |
A computer-aided design method and apparatus for compacting semiconductor circuit layouts to meet a specified set of design rules begins by fracturing a specified circuit layout into a set of trapezoids and storing the resulting cells in a database identifying the boundaries of each cell, and the cell adjacent each boundary. The method additionally includes a procedure for minimizing wire lengths in the compacted layout. Non-empty cells are identified as being of specific materials, and empty spaces between cells are represented. For each cell boundary, the database also stores data representing the boundary edge's end points. Neighboring cells on the same and related layers of the circuit layout share edges in the database. When a point on an edge of a cell is moved, the edge of each neighboring cell that shares that point is also moved. To adjust a circuit layout, the cells in the layout are processes in a sorted order. For each cell, width and spacing design rules are applied to first and second edges of the cell, which may result in movement of the cell and/or adjustment of the cell's width. An adjacent cell adjustment process conforms cells shared points with the adjusted cell. Once the compaction procedure is carried out in a positive x-direction, the coordinates are reversed and it is carried out again in a second pass. The compaction method is performed once for x-direction compaction and once for y-direction compaction. The wire minimization includes determining whether the second edges have been moved in the second pass, and if so applying the width rules to the first edges to minimize the length of wire represented by the width of the cell having the adjusted edges. The method sizes gate cells of transistors differently from other cells by maintaining the former at predetermined dimensions, with a user-definable override to resize transistors to a percentage of the predetermined dimensions.
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