发明名称 DATA PROCESSOR WITH CACHE BUFFER
摘要 PURPOSE:To obtain a data processor in which mismatching between inputted/ outputted data and data stored in a cache buffer can be prevented from occurring even when the data is inputted/outputted by bypassing the cache buffer. CONSTITUTION:This processor is equipped with a mismatching state can-cellation part 12 which copies the data between a buffer 13 for application program and a cache buffer area 5 when the cache buffer area 5 is bypassed when an application program 11 inputs/outputs the data to a block type device 10 and the mismatching between the data inputted/outputted actually and the one stored in the cache buffer area 5 occurs, and a selection condition holding part 3 which holds a selection condition whether or not the cache buffer area 5 should be bypassed when the data is inputted/outputted.
申请公布号 JPH07160582(A) 申请公布日期 1995.06.23
申请号 JP19930305294 申请日期 1993.12.06
申请人 MITSUBISHI ELECTRIC CORP 发明人 KISUKI YASUHISA
分类号 G06F11/00;G06F12/08;(IPC1-7):G06F12/08 主分类号 G06F11/00
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