A memory system for a data processor which includes a single chip integer unit (10), an array processor such as a floating point unit (20), a main memory (27) and a split level cache. The split level cache includes an on-chip, fast data cache (12) with low latency for use by the integer unit (10) for loads and stores of integer and address data and an off-chip, pipelined global cache (14) for storing arrays of data such as floating point data for use by the array processor and integer and address data for refilling the data cache. Coherence between the data cache (12) and global cache (14) is maintained by writing through to the global cache during integer stores. Data cache words are invalidated when data is written to the global cache during an array processor store.
