发明名称 |
Double-row address decoding and selection circuitry for an electrically erasable and programmable non-volatile memory device with redundancy, particularly for flash EEPROM devices. |
摘要 |
<p>A plurality of identical circuit blocks (PG0-PG15) is supplied with address signals (A0-A3,A0N-A3N) and each one generating a respective selection signal (P0-P15) which is activated by a particular logic configuration of said address signals (A0-A3,A0N-A3N) for the selection of a particular row (WL0-WL15) of the matrix; each one of said circuit blocks (PG0-PG15) also generates a carry-out signal (C00-C015) which is supplied to a carry-in input (CI0-CI15) of a following circuit block (PG0-PG15) and is activated when the respective selection signal (P0-P15) is activated; a first circuit block (PG0) of said plurality of circuit blocks (PG0-PG15) has the respective carry-in input (C10) connected to a reference voltage (GND); each of said circuit blocks (PG0-PG15) is also supplied with a control signal (E), which is activated by a control circuitry (6) of the memory device when, during a preprogramming operation preceding an electrical erasure of the memory device, a defective row (WL0-WL15) is addressed, to enable the activation of the respective selection signal (P0-P15) if the carry-out (C00-C014) signal supplying the respective carry-in input (CI1-CI15) is activated, so that two adjacent rows (WL0-WL15) can be simultaneously selected. <IMAGE></p> |
申请公布号 |
EP0658903(A1) |
申请公布日期 |
1995.06.21 |
申请号 |
EP19930830504 |
申请日期 |
1993.12.15 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
GOLLA, CARLA MARIA;OLIVO, MARCO |
分类号 |
G11C17/00;G11C8/12;G11C16/06;G11C16/08;G11C29/00;G11C29/04;(IPC1-7):G11C8/00;G06F11/20 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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