Databus architecture for accelerated column access in RAM.

摘要

The method of writing or reading a semiconductor random access memory (DRAM or SRAM) having several sense amplifiers connected to bit lines and having data bus read and write amplifiers, involves providing a pair of data buses for access by each sense amplifier and each read and write amplifier. One data bus is read from or written to while precharging the other data bus during a first read or write cycle. Data is read from or written to the other data bus while precharging the first data bus in a second read or write cycle following the first read or write cycle. The two cycles are consecutive odd and even time periods derived from a clock. A column address is input for each odd and even time period.