发明名称 Parallel path variable length decoding for video signals
摘要 A digital data processing system receives compressed variable length encoded digital data in the form of variable length codewords in contiguous variable speed Blocks of data. The boundary signals between adjacent codewords are determined and a demultiplexer sequentially sorts the serial digital data among a plurality of parallelly connected buffers for reducing the bit read speed of the buffers. A corresponding plurality of variable length decoders decodes the data from the buffers and outputs the data in parallel form to a multiplexer where it is reassembled into a serial expanded data stream. The incoming data includes selector information in fixed length headers that are separated, buffered and variable length decoded for controlling the demultiplexer. In one aspect of the invention, the data is sorted into substantially equal sized groups of integral codewords for equalizing the loading of the parallel buffers. In another aspect of the invention, the Block boundary marker signals are processed through much smaller auxiliary buffers using counters to keep track of the Block boundary marker signals for synchronization with the data flowing through the buffers.
申请公布号 US5424733(A) 申请公布日期 1995.06.13
申请号 US19930018668 申请日期 1993.02.17
申请人 ZENITH ELECTRONICS CORP. 发明人 FIMOFF, MARK;LAUD, TIMOTHY G.;LEE, RONALD B.
分类号 H03M7/42;H04N7/26;(IPC1-7):H03M7/42 主分类号 H03M7/42
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