| 摘要 |
The buffer is manufactured by forming a P well 1 (12) and a P well 2 (15) on the N substrate (11) between the P wells (12,13) to separate the P well 1 from the P well 2, forming an N well 1 (14) into the P well 1 (12), forming a pull-up PMOS transistor into the N well 1 (14), forming a pull-down NMOS transistor into the P well 2 (13), and forming a P+ region (16") into the P well 1 (12) to connect the region (16") to a Vss, thereby forming a triple-well structure to have a latch-up free charactristic.
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