发明名称 RAM DETECTION CONFIGURATION USING FERROELECTRIC CONTAINING BIT-LINE CAPACITY SEPARATION
摘要 PURPOSE: To reduce a spiking and an increase in an operating current of a sense amplifier in operation by providing a circuit for an electrical separation between a load capacitance and the sense amplifier. CONSTITUTION: A separation circuit 13 provided in a column 101 of a ferroelectric memory array circuit acts to electrically separate a first area of a bit line 26 connected to an array part 14 of ferroelectric memory cells 20 from a second area of a bit line 26' connected to a load capacitor 12. This circuit 13 matches with both operations of non-volatile ferroelectric memory and volatile dynamic memory, and reduces spiking and its increase of an operation current caused by a bit line capacity necessary for an active operation of a sense amplifier 16 in the ferroelectric memory. Further, it is preferable for the circuit 13 to use the sense amplifier 16, a current terminal connected with the memory cells 20 and the capacitor 12, and a switching transistor having a gate receiving a load separation signal.
申请公布号 JPH07147094(A) 申请公布日期 1995.06.06
申请号 JP19940133203 申请日期 1994.06.15
申请人 RAMUTORON INTERNATL CORP 发明人 UENNFUU CHIYAAN;BURETSUTO MEDOUSU
分类号 G11C14/00;G11C11/22;H01L21/8242;H01L21/8246;H01L27/10;H01L27/105;H01L27/108 主分类号 G11C14/00
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